Research Page of Yuanfang Hu
I recently graduated from Computer Science and Engineering Department (CSE), University of California, San Diego in Feb 2007. The topic of my PhD thesis is:
On-Chip Interconnection Architecture Optimization Using a Multicommodity Flow Approach,
which was done under the direction of Prof. Chung-Kuan Cheng.
- Y. Hu, Y. Zhu, H. Chen, C.K. Cheng, "Communication Latency
Aware Low Power Network-on-Chip Synthesis Through Topology
Exploration and Wire Style Optimization", submitted.
- S. Zhou, Y. Zhu, Y. Hu, R. Graham, M. Hutton, C.K. Cheng,
"Timing Model Reduction for Hierarchical Timing Analysis",
International. Conference on Computer Aided Design, 2006
- Y. Hu, Y. Zhu, H. Chen, C.K. Cheng, "Communication Latency Aware Low Power NoC Synthesis", Design Automation Conference, 2006
- Y. Hu, H. Chen, Y. Zhu, A. A. Chien, C.K. Cheng, "Physical Synthesis of Energy-Efficient NoCs Through Topology Exploration and Wire Style Optimization", International Conference on Computer Design, 2005
- J. Weinberg, A. Jagatheesan, A. Ding, M. Faerman, Y. Hu. "Gridflow Description, Query, and Execution at SCEC using the SDSC Matrix", International Symposium on High-Performance Distributed Computing, 2004
- S. Narayanasamy, Y. Hu, S. Sair, B. Calder. "An Instruction Scheduling Co-Processor for Adaptive VLIW Schedules", International Conference on High Performance Computer Architecture, 2004
- S. Sair, Y. Hu, T. Sherwood, B. Calder. "Optimized Trace Binaries for Architectural Evaluation", UCSD Technical report CS2002-0711, 2002
- Y. Hu, S. Zhang, W. Jiang. "Applying Object-Oriented Method to CSIE System", International Conference on Technology on Object-Oriented Languages and Systems, 1999